113 search results - page 17 / 23 » Architectural-Level Fault Tolerant Computation in Nanoelectr... |
ICPP
2002
IEEE
14 years 13 days ago
2002
IEEE
In this paper, we formulate the array robustness theorems (ARTs) for efficient computation and communication on faulty arrays. No hardware redundancy is required and no assumptio...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, fo...
EDCC
2008
Springer
13 years 9 months ago
2008
Springer
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...
FOCS
2008
IEEE
14 years 1 months ago
2008
IEEE
We design efficient protocols for processors to extract private randomness over a network with Byzantine faults, when each processor has access to an independent weakly-random n-...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Solving optimally large instances of combinatorial optimization problems requires a huge amount of computational resources. In this paper, we propose an adaptation of the parallel...