127 search results - page 7 / 26 » Architecture Independent Massive Parallelization of Divide-a... |
ARC
2008
Springer
13 years 10 months ago
2008
Springer
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
EPS
1995
Springer
14 years 4 days ago
1995
Springer
PANIC (Parallelism And Neural networks In Classifier systems) is a parallel system to evolve behavioral strategies codified by sets of rules. It integrates several adaptive techni...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
SPAA
1992
ACM
14 years 19 days ago
1992
ACM
A global barrier synchronizes all processors in a parallel system. This paper investigates algorithms that allow disjoint subsets of processors to synchronize independently and in...
ICRA
2010
IEEE
13 years 7 months ago
2010
IEEE
— The latency of a perception system is crucial for a robot performing interactive tasks in dynamic human environments. We present MOPED, a fast and scalable perception system fo...