218 search results - page 10 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
ISCA
1997
IEEE
14 years 1 months ago
1997
IEEE
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
DAC
2004
ACM
14 years 2 months ago
2004
ACM
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....
MICRO
2010
IEEE
13 years 7 months ago
2010
IEEE
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
FPL
2003
Springer
14 years 2 months ago
2003
Springer
In this paper we propose a design space exploration method targeting reconfigurable architectures that takes place at the algorithmic level and aims to rapidly highlight architect...
DAC
2005
ACM
14 years 10 months ago
2005
ACM
Device and interconnect fabrics at the nanoscale will have a density of defects and susceptibility to transient faults far exceeding those of current silicon technologies. In this...