218 search results - page 34 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
ICCD
2007
IEEE
14 years 6 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
HPCC
2005
Springer
14 years 2 months ago
2005
Springer
Nowadays the success of many e-commerce applications, such as on-line banking, depends on their reliability, robustness and security. Designing a web server architecture that keep...
ICDE
2010
IEEE
14 years 8 months ago
2010
IEEE
Abstract-- Field-programmable gate arrays (FPGAs) can provide performance advantages with a lower resource consumption (e.g., energy) than conventional CPUs. In this paper, we show...
CODES
2002
IEEE
14 years 1 months ago
2002
IEEE
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
ASPDAC
2006
ACM
14 years 3 months ago
2006
ACM
- This paper presents an H.264/AVC baseline profile decoder based on a SoC platform design methodology. The overall decoding throughput is increased by optimized software and a ded...