218 search results - page 6 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
TVLSI
2011
13 years 2 months ago
2011
—Communication costs, which have the potential to throttle design performance as scaling continues, are mathematically modeled and compared for various pipeline methodologies. Fi...
IBERAMIA
1998
Springer
13 years 12 months ago
1998
Springer
This paper 1 attempts to characterise a unifying overview of the practice of software engineers, AI designers, developers of evolutionary forms of computation, designers of adapti...
ITC
2000
IEEE
14 years 3 days ago
2000
IEEE
—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, ...
ASYNC
2003
IEEE
14 years 1 months ago
2003
IEEE
Parameterized first-order models for throughput, energy, and bandwidth are presented in this paper. Models are developed for many common pipeline methodologies, including clocked...