1381 search results - page 13 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
GLOBECOM
2006
IEEE
14 years 2 months ago
2006
IEEE
— Implementing a multi-tone (MT) architecture for high-speed backplane electrical links is difficult given the tight power and complexity constraints in this application. This pa...
ISPD
2010
ACM
14 years 2 months ago
2010
ACM
As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of onchip data th...
CODES
2006
IEEE
14 years 2 months ago
2006
IEEE
In deep sub-micron technology, the crosstalk effect between adjacent wires has become an important issue, especially between long on-chip buses. This effect leads to the increas...
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruct...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
The increasing demand for FPGAs and reconfigurable hardware targeting high performance low power applications has lead to an increasing requirement for new high performance reconf...