1381 search results - page 19 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
DATE
2003
IEEE
14 years 1 months ago
2003
IEEE
: Over the years, many design methodologies/tools and layout architectures have been developed for datapath-oriented designs. One commonly used approach for high-speed datapath des...
MTDT
2003
IEEE
14 years 1 months ago
2003
IEEE
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
TVLSI
2008
13 years 7 months ago
2008
Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is ra...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
1 Soft errors induced by radiation are an increasing problem in the microelectronic field. Although traditional models estimate the reliability of memories suffering Single Event U...