1381 search results - page 42 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
FPGA
1997
ACM
14 years 7 days ago
1997
ACM
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
ICCD
2007
IEEE
14 years 5 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
ICS
1999
Tsinghua U.
14 years 10 days ago
1999
Tsinghua U.
Supercomputer performance is highly dependent on its interconnection subsystem design. In this paper we study how di erent architectural approaches for router design impact into s...
WWW
2005
ACM
14 years 8 months ago
2005
ACM
Design of high performance Web servers has become a recent research thrust to meet the increasing demand of networkbased services. In this paper, we propose a new Web server archi...