1381 search results - page 78 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
ASPDAC
2007
ACM
14 years 5 days ago
2007
ACM
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
HOTI
2002
IEEE
14 years 1 months ago
2002
IEEE
High-performance input-queued switches require highspeed scheduling algorithms while maintaining good performance. Various round-robin scheduling algorithms for Virtual Output Que...
CLUSTER
2002
IEEE
14 years 1 months ago
2002
IEEE
Clusters of workstations have emerged as an important platform for building cost-effective, scalable, and highlyavailable computers. Although many hardware solutions are available...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
HOTI
2005
IEEE
14 years 1 months ago
2005
IEEE
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...