1381 search results - page 79 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
Future inter- and intra-ULSI interconnect systems demand extremely high data rates as well as bi-directional multi-I/O concurrent service, re-configurable computing/processing arc...
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper, we present a novel hybrid multiplier architecture that has the regularity of linear array multipliers and the performance of tree multipliers and is highly scalable...
DAC
2000
ACM
14 years 16 days ago
2000
ACM
Datapath design is one of the most critical elements in the design of a high performance microprocessor. However datapath design is typically done manually, and is often custom st...
ICESS
2007
Springer
14 years 2 months ago
2007
Springer
The performance of existing adders varies widely in their speed and area requirements, which in turn sometimes makes designers pay a high cost in area especially when the delay req...
DAC
1999
ACM
14 years 15 days ago
1999
ACM
Dual threshold technique has been proposed to reduce leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical p...