1381 search results - page 90 / 277 » Architecture and Design of a High Performance SRAM for SOC D... |
FPL
2006
Springer
13 years 12 months ago
2006
Springer
Emerging embedded System-on-Chip (SoC) platforms are increasingly becoming multiprocessor architectures. The advances in the FPGA chip technology make the implementation of such a...
DATE
2010
IEEE
14 years 16 days ago
2010
IEEE
We have proposed (, )-based flow regulation to reduce delay and backlog bounds in SoC architectures, where bounds the traffic burstiness and the traffic rate. The regulation is co...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements br...
GLVLSI
2010
IEEE
14 years 1 months ago
2010
IEEE
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (B...
MOBIHOC
2009
ACM
14 years 8 months ago
2009
ACM
In this paper, we present the architecture of a highly configurable multi-input multi?output (MIMO) orthogonal frequency division multiple access (OFDMA) platform. The platform is...