130 search results - page 17 / 26 » Architecture and Evaluation of an Asynchronous Array of Simp... |
ISCA
1998
IEEE
14 years 20 days ago
1998
IEEE
The design challenge for large-scale multiprocessors is (1) to minimize communication overhead, (2) allow communication to overlap computation, and (3) coordinate the two without ...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
CASES
2005
ACM
13 years 10 months ago
2005
ACM
In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) communication architecture (the fabric that integrates system components and carries the comm...
DAC
2004
ACM
14 years 9 months ago
2004
ACM
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
SPAA
2006
ACM
14 years 2 months ago
2006
ACM
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...