75 search results - page 12 / 15 » Architecture and Hardware for Scheduling Gigabit Packet Stre... |
TON
2010
13 years 2 months ago
2010
Abstract--A framework for designing feedback-based scheduling algorithms is proposed for elegantly solving the notorious packet missequencing problem of a load-balanced switch. Unl...
ISSS
1995
IEEE
13 years 11 months ago
1995
IEEE
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
CGO
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Multicore systems have not only become ubiquitous in the desktop and server worlds, but are also becoming the standard in the embedded space. Multicore offers programabi...
ISSS
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been dev...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Network-on-Chips (NoCs) are likely to become a critical shared resource in future many-core processors. The challenge is to develop policies and mechanisms that enable multiple ap...