75 search results - page 6 / 15 » Architecture and Hardware for Scheduling Gigabit Packet Stre... |
MICRO
1993
IEEE
13 years 11 months ago
1993
IEEE
Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents some results of our investigation into ways to modify MIM...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
FPL
2006
Springer
13 years 11 months ago
2006
Springer
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we introduce a new task model that is specifically targeted towards representing stream processing applications. Examples of such applications are those involved in...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...