This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between spice le...
Peter J. Vancorenland, Philippe Coppejans, Wouter ...
Abstract. In this article we present a low-cost coprocessor for smartcards which supports all necessary mathematical operations for a fast calculation of the Elliptic Curve Digital...
This paper presents an embedded FPGA–based architecture to compute navigation trajectories along a harmonic potential. The goals and obstacles may be changed during computation....
Cesar Torres-Huitzil, Bernard Girau, Amine M. Boum...
We advocate a network on silicon (NOS) as a hardware architecture to implement communication between IP cores in future technologies, and as a software model in the form of a prot...
Kees G. W. Goossens, Paul Wielage, Ad M. G. Peeter...
Two FPGA implementations of a Shape Adaptive Discrete Cosine Transform (SA-DCT) accelerator are presented in this paper: one PCI-based and the other AMBA-based. The former is used...
Andrew Kinane, Alan Casey, Valentin Muresan, Noel ...