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ICCAD
2002
IEEE
92views Hardware» more  ICCAD 2002»
14 years 6 months ago
Optimization of a fully integrated low power CMOS GPS receiver
This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between spice le...
Peter J. Vancorenland, Philippe Coppejans, Wouter ...
CHES
2004
Springer
155views Cryptology» more  CHES 2004»
14 years 3 months ago
A Low-Cost ECC Coprocessor for Smartcards
Abstract. In this article we present a low-cost coprocessor for smartcards which supports all necessary mathematical operations for a fast calculation of the Elliptic Curve Digital...
Harald Aigner, Holger Bock, Markus Hütter, Jo...
RECONFIG
2008
IEEE
122views VLSI» more  RECONFIG 2008»
14 years 4 months ago
Embedded Harmonic Control for Trajectory Planning in Large Environments
This paper presents an embedded FPGA–based architecture to compute navigation trajectories along a harmonic potential. The goals and obstacles may be changed during computation....
Cesar Torres-Huitzil, Bernard Girau, Amine M. Boum...
DATE
2002
IEEE
108views Hardware» more  DATE 2002»
14 years 2 months ago
Networks on Silicon: Combining Best-Effort and Guaranteed Services
We advocate a network on silicon (NOS) as a hardware architecture to implement communication between IP cores in future technologies, and as a software model in the form of a prot...
Kees G. W. Goossens, Paul Wielage, Ad M. G. Peeter...
FPT
2005
IEEE
133views Hardware» more  FPT 2005»
14 years 3 months ago
FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator
Two FPGA implementations of a Shape Adaptive Discrete Cosine Transform (SA-DCT) accelerator are presented in this paper: one PCI-based and the other AMBA-based. The former is used...
Andrew Kinane, Alan Casey, Valentin Muresan, Noel ...