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ASAP
2004
IEEE
127views Hardware» more  ASAP 2004»
14 years 15 days ago
A Public-Key Cryptographic Processor for RSA and ECC
We describe a general-purpose processor architecture for accelerating public-key computations on server systems that demand high performance and flexibility to accommodate large n...
Hans Eberle, Nils Gura, Sheueling Chang Shantz, Vi...
HICSS
2003
IEEE
148views Biometrics» more  HICSS 2003»
14 years 2 months ago
Managing Multimedia Traffic in IP Integrated over Differentiated Services: SIP dynamic signaling inter-working
The current IETF standardization work has highlighted the feasibility of providing the users with a QoS network architecture in the framework of Integrated Services over Different...
Stefano Giordano, M. Mancino, A. Martucci, Saverio...
ISCA
2008
IEEE
170views Hardware» more  ISCA 2008»
14 years 3 months ago
Polymorphic On-Chip Networks
As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We beg...
Martha Mercaldi Kim, John D. Davis, Mark Oskin, To...
FPL
2007
Springer
190views Hardware» more  FPL 2007»
14 years 2 months ago
The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems
Today’s heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of thes...
Andreas Herrholz, Frank Oppenheimer, Philipp A. Ha...
IPPS
2006
IEEE
14 years 2 months ago
Multi-clock pipelined design of an IEEE 802.11a physical layer transmitter
Among different wireless LAN technologies 802.11a has recently become popular due to its high throughput, large system capacity, and relatively long range. In this paper, we prop...
Maryam Mizani, Daler N. Rakhmatov