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» Architecture and synthesis for multi-cycle communication
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ISSS
1998
IEEE
120views Hardware» more  ISSS 1998»
13 years 12 months ago
Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation
Designing a cost effective superscalar architecture for x86 compatible microprocessors is a challenging task in terms of both technical difficulty and commercial value. One of the...
Ing-Jer Huang, Ping-Huei Xie
IESS
2007
Springer
165views Hardware» more  IESS 2007»
14 years 1 months ago
Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
Ilya Issenin, Nikil Dutt
IPCCC
2005
IEEE
14 years 1 months ago
Cluster-based input/output trace synthesis
I/O traces are crucial for understanding the performance of new storage architectures. Unfortunately, traces are extremely bursty and difficult to characterize. They are large, d...
Bo Hong, Tara M. Madhyastha, B. Zhang
SOSP
1993
ACM
13 years 9 months ago
The Information Bus - An Architecture for Extensible Distributed Systems
Research can rarely be performed on large-scale, distributed systems at the level of thousands of workstations. In this paper, we describe the motivating constraints, design princ...
Brian M. Oki, Manfred Pflügl, Alex Siegel, Da...
DAC
2009
ACM
14 years 8 months ago
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power c...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...