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ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
14 years 2 months ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
ANSS
1999
IEEE
14 years 1 months ago
DYANA: An Environment for Embedded System Design and Analysis
The results presented here are based on many years of experience of development and application of DYANA
Ruslan L. Smeliansky, Anatoly G. Bakhmurov, A. P. ...
AAAI
2010
13 years 10 months ago
Computationally Feasible Automated Mechanism Design: General Approach and Case Studies
In many multiagent settings, a decision must be made based on the preferences of multiple agents, and agents may lie about their preferences if this is to their benefit. In mechan...
Mingyu Guo, Vincent Conitzer
TOG
2012
206views Communications» more  TOG 2012»
11 years 11 months ago
Beady: interactive beadwork design and construction
We introduce the interactive system “Beady” to assist the design and construction of customized 3D beadwork. The user first creates a polygonal mesh model called the design m...
Yuki Igarashi, Takeo Igarashi, Jun Mitani
FCCM
2008
IEEE
160views VLSI» more  FCCM 2008»
14 years 3 months ago
Facilitating Processor-Based DPR Systems for non-DPR Experts
Currently, only Xilinx Field Programmable Gate Arrays (FPGAs) support Dynamic Partial Reconfiguration (DPR). While there is currently some Computer Aided Design (CAD) tool support...
Edward Chen, William A. Gruver, Dorian Sabaz, Lesl...