643 search results - page 3 / 129 » Architectures for function evaluation on FPGAs |
FPL
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. Function evaluation is at the core of many compute-intensive applications which perform well on reconfigurable platforms. Yet, in order to implement function evaluation ...
FPL
2001
Springer
14 years 5 days ago
2001
Springer
This paper presents parameterized module-generators for pipelined function evaluation using lookup tables, adders, shifters and multipliers. We discuss trade-offs involved between...
FPGA
2003
ACM
14 years 27 days ago
2003
ACM
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contri...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...