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ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
14 years 2 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...
IHIS
2005
ACM
14 years 2 months ago
An architecture for the interoperability of workflow models
The goal of this work is to contribute to the field of interoperability of Workflow models. To achieve this interoperability, we have built a generic architecture that s three lev...
Salah Hamri, Mahmoud Boufaïda, Nacer Boudjlid...
ASPLOS
2010
ACM
14 years 3 months ago
Flexible architectural support for fine-grain scheduling
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...
Daniel Sanchez, Richard M. Yoo, Christos Kozyrakis
DAGSTUHL
2003
13 years 10 months ago
Traceability and Evaluation in Scenario Analysis by Use Case Maps
The Use Case Map (UCM) scenario notation has some strong features related to rapid capture and evaluation of requirements models. In this paper, we explain how a UCM model was deve...
Dorin Bogdan Petriu, Daniel Amyot, C. Murray Woods...
MM
2005
ACM
215views Multimedia» more  MM 2005»
14 years 2 months ago
OpenVIDIA: parallel GPU computer vision
Graphics and vision are approximate inverses of each other: ordinarily Graphics Processing Units (GPUs) are used to convert “numbers into pictures” (i.e. computer graphics). I...
James Fung, Steve Mann