67 search results - page 10 / 14 » Array-of-arrays architecture for parallel floating point mul... |
DATE
2006
IEEE
14 years 4 months ago
2006
IEEE
In traditional parallel co-simulation approaches, the simulation speed is heavily limited by time synchronization overhead between simulators and idle time caused by data dependen...
COMPUTING
2004
13 years 10 months ago
2004
The presented image registration method uses a regularized gradient flow to correlate the intensities in two images. Thereby, an energy functional is successively minimized by des...
ISCA
2010
IEEE
14 years 2 months ago
2010
IEEE
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
ISCAS
2007
IEEE
14 years 4 months ago
2007
IEEE
—The paper presents architecture and synthesis results for an organic computing hardware for smart CMOS camera chips. The organic behavior in the chip hardware is based on distri...
ATAL
2005
Springer
14 years 3 months ago
2005
Springer
One aspect of rational behavior is that agents can pursue multiple goals in parallel. Current BDI theory and systems do not provide a theoretical or architectural framework for de...