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FPL
2005
Springer
226views Hardware» more  FPL 2005»
14 years 1 months ago
A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC
A parallel MPEG-4 Simple Profile encoder for FPGA based multiprocessor System-on-Chip (SOC) is presented. The goal is a computationally scalable framework independent of platform....
Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko...
ASPDAC
2000
ACM
104views Hardware» more  ASPDAC 2000»
13 years 12 months ago
Design of digital neural cell scheduler for intelligent IB-ATM switch
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
J.-K. Lee, Seung-Min Lee, Mike Myung-Ok Lee, D.-W....
DATE
2010
IEEE
121views Hardware» more  DATE 2010»
14 years 18 days ago
Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems
—In this paper, we present a method to analyze different implementations of stream-based applications on heterogeneous multiprocessor systems. We take both resource usage and per...
Sven van Haastregt, Eyal Halm, Bart Kienhuis
ISCAS
2003
IEEE
148views Hardware» more  ISCAS 2003»
14 years 23 days ago
Hybrid neural network architecture for age identification of ancient Kannada scripts
Wide research has been carried out and is still taking place in the field of character recognition of handwritten English characters. Recognizing English characters is much simple...
Harish K. Kashyap, Bansilal, P. Arun Koushik
ANCS
2006
ACM
14 years 1 months ago
Design of a web switch in a reconfigurable platform
The increase of the web traffic has created the need for web switches that are able to balance the traffic to the server farms based on their contents (e.g. layer 7 switching). In...
Christoforos Kachris, Stamatis Vassiliadis