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HPCA
2009
IEEE
14 years 10 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
VLSID
2004
IEEE
125views VLSI» more  VLSID 2004»
14 years 10 months ago
Energy-Optimizing Source Code Transformations for OS-driven Embedded Software
The increasing software content of battery-powered embedded systems has fueled much interest in techniques for developing energyefficient embedded software. Source code transforma...
Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj...
HPCA
2006
IEEE
14 years 10 months ago
Efficient instruction schedulers for SMT processors
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
Joseph J. Sharkey, Dmitry V. Ponomarev
MOBIHOC
2008
ACM
14 years 9 months ago
Construction algorithms for k-connected m-dominating sets in wireless sensor networks
A Connected Dominating Set (CDS) working as a virtual backbone is an effective way to decrease the overhead of routing in a wireless sensor network. Furthermore, a kConnected m-Do...
Yiwei Wu, Yingshu Li
ICPP
2009
IEEE
14 years 4 months ago
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
Yolanda Becerra, Vicenç Beltran, David Carr...