1524 search results - page 111 / 305 » Assessing Instructional Technology |
EMISA
2010
Springer
13 years 4 months ago
2010
Springer
Abstract. When assessing the usability of BPM technologies enterprises have to rely on vendor promises or qualitative data rather than on empirical or experimental research. To add...
HPCA
2003
IEEE
14 years 9 months ago
2003
IEEE
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...
DCC
2002
IEEE
14 years 8 months ago
2002
IEEE
With the emergence of software delivery platforms such as Microsoft's .NET, code compression has become one of the core enabling technologies strongly affecting system perfor...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
APCSAC
2006
IEEE
14 years 3 months ago
2006
IEEE
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...