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» Assessing Instructional Technology
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ICCD
2006
IEEE
107views Hardware» more  ICCD 2006»
14 years 7 months ago
Design and Implementation of the TRIPS Primary Memory System
Abstract— In this paper, we describe the design and implementation of the primary memory system of the TRIPS processor. To match the aggressive execution bandwidth and support hi...
Simha Sethumadhavan, Robert G. McDonald, Rajagopal...
ICCD
2004
IEEE
158views Hardware» more  ICCD 2004»
14 years 7 months ago
An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing
A programmable parallel digital signal processor (DSP) core for embedded applications is presented which combines the concepts of single instruction stream over multiple data stre...
Liang Han, Jie Chen, Chaoxian Zhou, Ying Li, Xin Z...
CHI
2010
ACM
14 years 5 months ago
Layered elaboration: a new technique for co-design with children
As technology for children becomes more mobile, social, and distributed, our design methods and techniques must evolve to better explore these new directions. This paper reports o...
Greg Walsh, Allison Druin, Mona Leigh Guha, Elizab...
DATE
2009
IEEE
92views Hardware» more  DATE 2009»
14 years 5 months ago
Using randomization to cope with circuit uncertainty
—Future computing systems will feature many cores that run fast, but might show more faults compared to existing CMOS technologies. New software methodologies must be adopted to ...
Hamid Safizadeh, Mohammad Tahghighi, Ehsan K. Arde...
DAMON
2009
Springer
14 years 4 months ago
Frequent itemset mining on graphics processors
We present two efficient Apriori implementations of Frequent Itemset Mining (FIM) that utilize new-generation graphics processing units (GPUs). Our implementations take advantage ...
Wenbin Fang, Mian Lu, Xiangye Xiao, Bingsheng He, ...