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ASPDAC
2006
ACM
110views Hardware» more  ASPDAC 2006»
14 years 3 months ago
Switching-activity driven gate sizing and Vth assignment for low power design
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 6 months ago
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems
Three dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a number of research efforts have addressed physical ...
Madhubanti Mukherjee, Ranga Vemuri
DBSEC
2010
137views Database» more  DBSEC 2010»
13 years 11 months ago
Constructing Key Assignment Schemes from Chain Partitions
Abstract. In considering a problem in access control for scalable multimedia formats, we have developed new methods for constructing a key assignment scheme. Our first contribution...
Jason Crampton, Rosli Daud, Keith M. Martin
ASPDAC
2004
ACM
93views Hardware» more  ASPDAC 2004»
14 years 3 months ago
Layer assignment for reliable system-on-package
—The routing environment for the new emerging mixed-signal System-on-Package (SOP) technology is more advanced than that of the conventional PCB or MCM technology – pins are lo...
Jacob R. Minz, Sung Kyu Lim
SLIP
2009
ACM
14 years 4 months ago
Integrated interlayer via planning and pin assignment for 3D ICs
As technology advances, 3D ICs are introduced for alleviating the interconnect problem coming with shrinking feature size and increasing integration density. In 3D ICs, one of the...
Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto