Switching-activity driven gate sizing and Vth assignment for low power design

Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Previous research regarding this problem focused on either minimizing dynamic power by gate sizing, or reducing leakage power by dual threshold voltage assignment on non-critical path. However, given a timing constraint, an optimization algorithm must be able to utilize gate sizing and threshold-voltage assignment interchangeably, in order to minimize total power consumption including dynamic and leakage power in active mode and leakage power in idle mode. We find that switchingactivity of a gate plays an important role in making decision as to choosing gate sizing or threshold-voltage assignment for performance improvement. For high switchingactivity gates, threshold-voltage assignment should be used while for low switching-activity gates, gate sizing should be utilized. We develop an algorithm to perform gat...

• Type: Conference
• Year: 2006
• Where: ASPDAC
• Authors: Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang
• Keywords: ASPDAC 2006, Leakage Power, Threshold-voltage Assignment, Timing Constraint