103 search results - page 4 / 21 » Asymmetric Memory Fences: Optimizing Both Performance and Im... |
HIPC
2009
Springer
13 years 6 months ago
2009
Springer
As the size of available datasets in various domains is growing rapidly, there is an increasing need for scaling data mining implementations. Coupled with the current trends in co...
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
IPPS
2000
IEEE
14 years 28 days ago
2000
IEEE
Abstract. Nested data-parallel programs often have large memory requirements due to their high degree of parallelism. Piecewise execution is an implementation technique used to min...
HIPEAC
2007
Springer
14 years 2 months ago
2007
Springer
The XScale processor family provides user-controllable independent configuration of CPU, bus, and memory frequencies. This feature introduces another handle for the code optimizat...
IWMM
2011
Springer
12 years 11 months ago
2011
Springer
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...