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CDES
2010
184views Hardware» more  CDES 2010»
13 years 5 months ago
Delay-Insensitive Cell Matrix
This paper describes the design of a delay-insensitive (DI) Cell Matrix. This architecture allows for massively parallel, self-determined operation and can be used to implement reg...
Scott Smith, David Roclin, Jia Di
TVLSI
2010
13 years 2 months ago
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
Zhiyi Yu, Bevan M. Baas
TVCG
2012
182views Hardware» more  TVCG 2012»
11 years 9 months ago
ISP: An Optimal Out-of-Core Image-Set Processing Streaming Architecture for Parallel Heterogeneous Systems
—Image population analysis is the class of statistical methods that plays a central role in understanding the development, evolution and disease of a population. However, these t...
Linh K. Ha, Jens Krüger, João Luiz Dih...
AINA
2003
IEEE
14 years 20 days ago
Server Scheduling Scheme for Asynchronous Cluster Video Server
In this paper, we propose an asynchronous cluster video server architecture, which is quite different from synchronous video server architecture in various aspects such as stripin...
Jianhua Sun, Hai Jin, Hao Chen, Zongfen Han
DAC
1999
ACM
14 years 8 months ago
Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems
Alex Kondratyev, Jordi Cortadella, Michael Kishine...