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» Asynchronous circuit design on reconfigurable devices
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ASYNC
2006
IEEE
122views Hardware» more  ASYNC 2006»
14 years 1 months ago
A Level-Crossing Flash Asynchronous Analog-to-Digital Converter
Distributed sensor networks, human body implants, and hand-held electronics have tight energy budgets that necessitate low power circuits. Most of these devices include an analog-...
Filipp Akopyan, Rajit Manohar, Alyssa B. Apsel
AHS
2006
IEEE
86views Hardware» more  AHS 2006»
14 years 1 months ago
An Efficient Technique for Preventing Single Event Disruptions in Synchronous and Reconfigurable Architectures
This paper presents a unique SEU (single Event Upset) mitigation technique based upon Temporal Data Sampling for synchronous circuits and configuration bit storage for programmabl...
Sajid Baloch, Tughrul Arslan, Adrian Stoica
CHES
2003
Springer
146views Cryptology» more  CHES 2003»
13 years 11 months ago
Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs
Abstract. Performance evaluation of the Advanced Encryption Standard candidates has led to intensive study of both hardware and software implementations. However, although plentifu...
François-Xavier Standaert, Gaël Rouvro...
DAC
2002
ACM
14 years 8 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
DATE
2008
IEEE
104views Hardware» more  DATE 2008»
14 years 2 months ago
Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters
– A new approach for diagnostic analysis of static errors in multi-step ADC based on the steepestdescent method is proposed. To set initial data, estimate the parameter update an...
Amir Zjajo, José Pineda de Gyvez