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» Automated Bus Generation for Multiprocessor SoC Design
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DAC
2009
ACM
14 years 8 months ago
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-K...
GTTSE
2007
Springer
14 years 1 months ago
Model Transformations for the Compilation of Multi-processor Systems-on-Chip
With the increase of amount of transistors which can be contained on a chip and the constant expectation for more sophisticated applications, the design of Systems-on-Chip (SoC) is...
Éric Piel, Philippe Marquet, Jean-Luc Dekey...
DATE
2009
IEEE
130views Hardware» more  DATE 2009»
14 years 1 months ago
Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA
—IP-XACT is a standard for describing intellectual property metadata for System-on-Chip (SoC) integration. Reesearchers have proposed visualizing and abstracting IP-XACT objects ...
Tero Arpinen, Tapio Koskinen, Erno Salminen, Timo ...
FMCAD
2006
Springer
13 years 10 months ago
Design for Verification of the PCI-X Bus
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...
Haja Moinudeen, Ali Habibi, Sofiène Tahar
DATE
2007
IEEE
126views Hardware» more  DATE 2007»
14 years 1 months ago
A future of customizable processors: are we there yet?
Customizable processors are being used increasingly often in SoC designs. During the past few years, they have proven to be a good way to solve the conflicting flexibility and p...
Laura Pozzi, Pierre G. Paulin