65 search results - page 6 / 13 » Automated Bus Generation for Multiprocessor SoC Design |
DAC
2008
ACM
14 years 8 months ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
– Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Bus matrix based com...
DATE
2003
IEEE
14 years 11 days ago
2003
IEEE
A system-on-chip lock cache (SoCLC) is an intellectual property (IP) core that provides effective lock synchronization in a heterogeneous multiprocessor shared-memory system-on-ac...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
This paper describes a novel engine, called PE-ICE (Parallelized Encryption and Integrity Checking Engine), enabling to guarantee confidentiality and integrity of data exchanged b...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processo...