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» Automated Design of Quantum Circuits
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GLVLSI
2008
IEEE
120views VLSI» more  GLVLSI 2008»
14 years 4 months ago
SAT-based equivalence checking of threshold logic designs for nanotechnologies
Novel nano-scale devices have shown promising potential to overcome physical barriers faced by complementary metaloxide semiconductor (CMOS) technology in future circuit design. H...
Yexin Zheng, Michael S. Hsiao, Chao Huang
DAC
2004
ACM
14 years 11 months ago
Profile-guided microarchitectural floorplanning for deep submicron processor design
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watew...
DAC
2005
ACM
14 years 11 months ago
Variations-aware low-power design with voltage scaling
We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system. We show that in the presence of pro...
Navid Azizi, Muhammad M. Khellah, Vivek De, Farid ...
ICCAD
2005
IEEE
104views Hardware» more  ICCAD 2005»
14 years 6 months ago
Design of DNA origami
— The generation of arbitrary patterns and shapes at very small scales is at the heart of our effort to miniaturize circuits and is fundamental to the development of nanotechnolo...
Paul W. K. Rothemund
DATE
2006
IEEE
140views Hardware» more  DATE 2006»
14 years 4 months ago
A hybrid framework for design and analysis of fault-tolerant architectures
It is anticipated that self assembled ultra-dense nanomemories will be more susceptible to manufacturing defects and transient faults than conventional CMOS-based memories, thus t...
Debayan Bhaduri, Sandeep K. Shukla, Deji Coker, Va...