The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
For present-day micro-electronic designs, it is becoming ever more important to accurately model substrate coupling effects. Basically, either a Finite Element Method (FEM) or a B...
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-sca...