119 search results - page 17 / 24 » Automated Modeling of Custom Digital Circuits for Test |
ANSS
2006
IEEE
14 years 2 months ago
2006
IEEE
Anomaly detection systems largely depend on user profile data to be able to detect deviation from normal activity. Most of this profile data is based on commands executed by use...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
ICCAD
2002
IEEE
14 years 5 months ago
2002
IEEE
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
DAC
2003
ACM
14 years 9 months ago
2003
ACM
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...