338 search results - page 51 / 68 » Automated Performance Prediction of Message-Passing Parallel... |
DAC
2009
ACM
14 years 9 months ago
2009
ACM
Exponentially rising cooling/packaging costs due to high power density call for architectural and software-level thermal management. Dynamic thermal management (DTM) techniques co...
JPDC
2000
13 years 8 months ago
2000
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
ALP
1992
Springer
14 years 17 days ago
1992
Springer
Rewriting is a computational paradigm that specifies the actions, but not the control. We introduce a hierarchical structure repreat a high level of abstraction, a form of control....
IEEEPACT
2009
IEEE
2009
IEEE
Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning
14 years 3 months ago
—Performance degradation of memory-intensive programs caused by the LRU policy’s inability to handle weaklocality data accesses in the last level cache is increasingly serious ...