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2007
IEEE
14 years 12 days ago
Identifying energy-efficient concurrency levels using machine learning
Abstract-- Multicore microprocessors have been largely motivated by the diminishing returns in performance and the increased power consumption of single-threaded ILP microprocessor...
Matthew Curtis-Maury, Karan Singh, Sally A. McKee,...
DAC
2003
ACM
14 years 9 months ago
Performance-impact limited area fill synthesis
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local ...
Yu Chen, Puneet Gupta, Andrew B. Kahng
SOFSEM
2010
Springer
14 years 5 months ago
Source Code Rejuvenation Is Not Refactoring
Programmers rely on programming idioms, design patterns, and workaround techniques to make up for missing programming language support. Evolving languages often address frequently ...
Peter Pirkelbauer, Damian Dechev, Bjarne Stroustru...
DAC
2008
ACM
14 years 9 months ago
Daedalus: toward composable multimedia MP-SoC design
Daedalus is a system-level design flow for the design of multiprocessor system-on-chip (MP-SoC) based embedded multimedia systems. It offers a fully integrated tool-flow in which ...
Hristo Nikolov, Mark Thompson, Todor Stefanov, And...
ICS
2009
Tsinghua U.
14 years 3 months ago
Adagio: making DVS practical for complex HPC applications
Power and energy are first-order design constraints in high performance computing. Current research using dynamic voltage scaling (DVS) relies on trading increased execution time...
Barry Rountree, David K. Lowenthal, Bronis R. de S...