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    DAC
    2002
    ACM
    95views Computer Architecture» more  DAC 2002»
    Can BDDs compete with SAT solvers on bounded model checking?
    14 years 10 months ago
    Can BDDs compete with SAT solvers on bounded model checking?
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    Gianpiero Cabodi, Paolo Camurati, Stefano Quer
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    DAC
    2002
    ACM
    86views Computer Architecture» more  DAC 2002»
    S-Tree: a technique for buffered routing tree synthesis
    14 years 10 months ago
    S-Tree: a technique for buffered routing tree synthesis
    Download  www.cs.uic.edu
    Milos Hrkic, John Lillis
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    DAC
    2002
    ACM
    123views Computer Architecture» more  DAC 2002»
    Implementing asynchronous circuits using a conventional EDA tool-flow
    14 years 10 months ago
    Implementing asynchronous circuits using a conventional EDA tool-flow
    Download  www.bcim.lsbu.ac.uk
    Christos P. Sotiriou
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    DAC
    2003
    ACM
    132views Computer Architecture» more  DAC 2003»
    Timing optimization of FPGA placements by logic replication
    14 years 10 months ago
    Timing optimization of FPGA placements by logic replication
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    Giancarlo Beraudo, John Lillis
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    DAC
    2003
    ACM
    100views Computer Architecture» more  DAC 2003»
    How to make efficient communication, collaboration, and optimization from system to chip
    14 years 10 months ago
    How to make efficient communication, collaboration, and optimization from system to chip
    Download  www.ssc.pe.titech.ac.jp
    Akira Matsuzawa
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