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DATE
2005
IEEE
99views Hardware» more  DATE 2005»
14 years 1 months ago
A New System Design Methodology for Wire Pipelined SoC
Wire Pipelining (WP) has been proposed in order to limit the impact of increasing wire delays. In general, the added pipeline elements alters the system such that architectural ch...
Mario R. Casu, Luca Macchiarulo
DAC
2003
ACM
14 years 9 months ago
Embedded intelligent SRAM
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage. We present an enhancement called Intelligent SRAM (ISRAM) that co...
Prabhat Jain, G. Edward Suh, Srinivas Devadas
IWEC
2004
13 years 9 months ago
From Artistry to Automation: A Structured Methodology for Procedural Content Creation
Procedural techniques will soon automate many aspects of content creation for computer games. We describe an efficient, deterministic, methodology for procedurally generating 3D ga...
Timothy Roden, Ian Parberry
ECOI
2010
117views more  ECOI 2010»
13 years 8 months ago
Ensemble extraction for classification and detection of bird species
Advances in technology have enabled new approaches for sensing the environment and collecting data about the world. Once collected, sensor readings can be assembled into data stre...
Eric P. Kasten, Philip K. McKinley, Stuart H. Gage
HPCA
1996
IEEE
14 years 4 days ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...