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IPPS
1998
IEEE
14 years 7 days ago
Design, Implementation and Evaluation of Parallel Pipelined STAP on Parallel Computers
This paper presents performance results for the design and implementation of parallel pipelined Space-Time Adaptive Processing (STAP) algorithms on parallel computers. In particul...
Alok N. Choudhary, Wei-keng Liao, Donald Weiner, P...
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 1 months ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
ISLPED
1996
ACM
68views Hardware» more  ISLPED 1996»
14 years 3 days ago
Energy-recovery CMOS for highly pipelined DSP designs
We compare the frequency-versus-power dissipation performance of two energy-recovery CMOS implementations to that of a conventional, supply-voltage-scaled design. The application ...
William C. Athas, W.-C. Liu, Lars J. Svensson
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
14 years 1 months ago
Systematic Figure of Merit Computation for the Design of Pipeline ADC
Ludovic Barrandon, S. Crand, Dominique Houzet