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ICCAD
2006
IEEE
147views Hardware» more  ICCAD 2006»
14 years 4 months ago
Analysis and modeling of CD variation for statistical static timing
Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much research has focused...
Brian Cline, Kaviraj Chopra, David Blaauw, Yu Cao
ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
14 years 1 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock
HICSS
2006
IEEE
163views Biometrics» more  HICSS 2006»
14 years 1 months ago
Learning Ranking vs. Modeling Relevance
The classical (ad hoc) document retrieval problem has been traditionally approached through ranking according to heuristically developed functions (such as tf.idf or bm25) or gene...
Dmitri Roussinov, Weiguo Fan
DAC
1999
ACM
13 years 12 months ago
ipChinook: an Integrated IP-based Design Framework for Distributed Embedded Systems
IPCHINOOK is a design tool for distributed embedded systems. It gains leverage from the use of a carefully chosen set of design ions that raise the level of designer interaction d...
Pai H. Chou, Ross B. Ortega, Ken Hines, Kurt Partr...
ASE
2005
137views more  ASE 2005»
13 years 7 months ago
Rewriting-Based Techniques for Runtime Verification
Techniques for efficiently evaluating future time Linear Temporal Logic (abbreviated LTL) formulae on finite execution traces are presented. While the standard models of LTL are i...
Grigore Rosu, Klaus Havelund