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ISICT
2003
13 years 9 months ago
On the automated implementation of modal logics used to verify security protocols
: Formal verification provides a rigid and thorough means of evaluating the correctness of cryptographic protocols so that even subtle defects can be identified. As the application...
Tom Coffey, Reiner Dojen, Tomas Flanagan
DAC
2007
ACM
14 years 8 months ago
Multi-Core Design Automation Challenges
The trend to multi-core chip designs presents new challenges for design automation, while the increased reuse of components may offer solutions. This paper describes some of the k...
John A. Darringer
ASE
2006
148views more  ASE 2006»
13 years 7 months ago
PLFaultCAT: A Product-Line Software Fault Tree Analysis Tool
Industry currently employs a product line approach to software development and deployment as a means to enhance quality while reducing development cost and time. This effort has cr...
Josh Dehlinger, Robyn R. Lutz
EURODAC
1990
IEEE
102views VHDL» more  EURODAC 1990»
13 years 11 months ago
Tools and devices supporting the pseudo-exhaustive test
: In this paper logical cells and algorithms are presented supporting the design of pseudo-exhaustively testable circuits. The approach is based on real hardware segmentation, inst...
Sybille Hellebrand, Hans-Joachim Wunderlich
DATE
2008
IEEE
112views Hardware» more  DATE 2008»
14 years 2 months ago
Tool Support for Incremental Failure Mode and Effects Analysis of Component-Based Systems
Failure Mode and Effects Analysis (FMEA) is a wellknown technique widely used for safety assessment in the area of safety-critical systems. However, FMEA is traditionally done man...
Jonas Elmqvist, Simin Nadjm-Tehrani