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ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
14 years 4 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
DAC
2005
ACM
14 years 8 months ago
Temperature-aware resource allocation and binding in high-level synthesis
Physical phenomena such as temperature have an increasingly important role in performance and reliability of modern process technologies. This trend will only strengthen with futu...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
CODES
2006
IEEE
14 years 1 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
FPL
2007
Springer
80views Hardware» more  FPL 2007»
14 years 1 months ago
A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize req...
Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi,...
ANCS
2005
ACM
14 years 1 months ago
High-throughput linked-pattern matching for intrusion detection systems
This paper presents a hardware architecture for highly efficient intrusion detection systems. In addition, a software tool for automatically generating the hardware is presented....
Zachary K. Baker, Viktor K. Prasanna