Precomputation is a recently proposed logic optimization technique which selectively disables the inputs of a sequential logic circuit, thereby reducing switching activity and pow...
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
The design of programmable logic architectures and supporting computer-aided design tools fundamentally requires both a good understanding of the combinatorial nature of netlist gr...
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
Abstract. Delay-Insensitive Sequential Processes is a structured, parallel programming language. It facilitates the clear, succinct and precise specification of the way an asynchro...
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...