101 search results - page 6 / 21 » Automatic Clock Abstraction from Sequential Circuits |
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for th...
ISLPED
1997
ACM
13 years 11 months ago
1997
ACM
New measures of peak power in the context of sequential circuits are proposed. This paper presents an automatic procedure to obtain very good lower bounds on these measures as wel...
FMCAD
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. We relate two well-studied methodologies in deductive verification of operationally modeled sequential programs, namely the use of inductive invariants and clock functio...
APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
Traditional approaches for sequential logic optimization include (1) explicit state-based techniques such as state minimization, (2) structural techniques such as retiming, and (3...