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DATE
2005
IEEE
118views Hardware» more  DATE 2005»
15 years 10 months ago
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach
In this paper, we present a methodology for customized communication architecture synthesis that matches the communication requirements of the target application. This is an impor...
Ümit Y. Ogras, Radu Marculescu
ERSA
2010
159views Hardware» more  ERSA 2010»
15 years 2 months ago
Acceleration of FPGA Fault Injection Through Multi-Bit Testing
SRAM-based FPGA devices are an attractive option for data processing on space-based platforms, due to high computational capabilities and a lower power envelope than traditional pr...
Grzegorz Cieslewski, Alan D. George, Adam Jacobs
DATE
2009
IEEE
100views Hardware» more  DATE 2009»
15 years 11 months ago
Increasing the accuracy of SAT-based debugging
Equivalence checking and property checking are powerful techniques to detect error traces. Debugging these traces is a time consuming design task where automation provides help. I...
André Sülflow, Görschwin Fey, C&e...
ICECCS
2009
IEEE
106views Hardware» more  ICECCS 2009»
15 years 11 months ago
Visual Comparison of Graphical Models
Collaborative development, incremental design and revision management require the ability to compare different versions of software artifacts. There are well-established approache...
Arne Schipper, Hauke Fuhrmann, Reinhard von Hanxle...
DSD
2009
IEEE
88views Hardware» more  DSD 2009»
15 years 2 months ago
A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor
Abstract--The implementation of an efficient result forwarding unit for asynchronous processors faces the problem of the inherent lack of synchronisation between result producer an...
Luis A. Tarazona, Doug A. Edwards, Luis A. Plana