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CAV
2001
Springer
154views Hardware» more  CAV 2001»
15 years 8 months ago
Automated Verification of a Randomized Distributed Consensus Protocol Using Cadence SMV and PRISM
We consider the randomized consensus protocol of Aspnes and Herlihy for achieving agreement among N asynchronous processes that communicate via read/write shared registers. The alg...
Marta Z. Kwiatkowska, Gethin Norman, Roberto Segal...
DATE
2007
IEEE
126views Hardware» more  DATE 2007»
15 years 10 months ago
A future of customizable processors: are we there yet?
Customizable processors are being used increasingly often in SoC designs. During the past few years, they have proven to be a good way to solve the conflicting flexibility and p...
Laura Pozzi, Pierre G. Paulin
ASPLOS
2006
ACM
15 years 10 months ago
Introspective 3D chips
While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexit...
Shashidhar Mysore, Banit Agrawal, Navin Srivastava...
ICCD
2004
IEEE
106views Hardware» more  ICCD 2004»
16 years 1 months ago
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction
Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduc...
Feng Gao, John P. Hayes
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
15 years 9 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen