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ISVLSI
2005
IEEE
169views VLSI» more  ISVLSI 2005»
15 years 9 months ago
High Performance Array Processor for Video Decoding
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
15 years 10 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
FCCM
2008
IEEE
160views VLSI» more  FCCM 2008»
15 years 10 months ago
Facilitating Processor-Based DPR Systems for non-DPR Experts
Currently, only Xilinx Field Programmable Gate Arrays (FPGAs) support Dynamic Partial Reconfiguration (DPR). While there is currently some Computer Aided Design (CAD) tool support...
Edward Chen, William A. Gruver, Dorian Sabaz, Lesl...
DAC
2006
ACM
16 years 5 months ago
Behavior and communication co-optimization for systems with sequential communication media
In this paper we propose a new communication synthesis approach targeting systems with sequential communication media (SCM). Since SCMs require that the reading sequence and writi...
Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zh...
EUROMICRO
2005
IEEE
15 years 9 months ago
Software Security Analysis - Execution Phase Audit
Code revision of a leading telecom product was performed, combining manual audit and static analysis tools. On average, one exploitable vulnerability was found for every 4000 line...
Bengt Carlsson, Dejan Baca