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CAV
2007
Springer
129views Hardware» more  CAV 2007»
15 years 10 months ago
BAT: The Bit-Level Analysis Tool
Abstract. While effective methods for bit-level verification of low-level properties exist, system-level properties that entail reasoning about a significant part of the design p...
Panagiotis Manolios, Sudarshan K. Srinivasan, Daro...
SASP
2008
IEEE
140views Hardware» more  SASP 2008»
15 years 10 months ago
An FPGA Design Space Exploration Tool for Matrix Inversion Architectures
— Matrix inversion is a common function found in many algorithms used in wireless communication systems. As FPGAs become an increasingly attractive platform for wireless communic...
Ali Irturk, Bridget Benson, Shahnam Mirzaei, Ryan ...
DATE
2008
IEEE
104views Hardware» more  DATE 2008»
15 years 10 months ago
A Novel Approach for EMI Design of Power Electronics
The placement of passive components significantly influences the EMI behavior of power electronic systems. Particularly filter components are affected by magnetic field coupling r...
Bernd Stube, Bernd Schröder, Eckart Hoene, An...
SAMOS
2007
Springer
15 years 10 months ago
FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder
Client-side diversification led the video-coding community to develop scalable video-codecs supporting efficient decoding at varying quality levels. This scalability has a lot of...
Hendrik Eeckhaut, Harald Devos, Philippe Faes, Mar...
ICCD
2001
IEEE
88views Hardware» more  ICCD 2001»
16 years 28 days ago
Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
Payam Heydari, Massoud Pedram