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KBSE
2002
IEEE
14 years 1 months ago
SeDiTeC - Testing Based on Sequence Diagrams
In this paper we present a concept for automated testing of object-oriented applications and a tool called SeDiTeC that implements these concepts for Java applications. SeDiTeC us...
Falk Fraikin, Thomas Leonhardt
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
14 years 1 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
RSP
2005
IEEE
162views Control Systems» more  RSP 2005»
14 years 2 months ago
SyCE: An Integrated Environment for System Design in SystemC
We present an integrated system design environment for SystemC, called SyCE. The system consists of several components for efficient analysis, verification and debugging of Syst...
Rolf Drechsler, Görschwin Fey, Christian Genz...
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
14 years 5 days ago
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an ...
Chulho Shin, Young-Taek Kim, Eui-Young Chung, Kyu-...
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
14 years 2 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...